CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 81.
49. lappuse
... compared with a same sized conventional direct mapped cache . The negative value stands for that the efficient cache consumes less energy than that of a conventional direct mapped cache . Compared with the conventional two - way set ...
... compared with a same sized conventional direct mapped cache . The negative value stands for that the efficient cache consumes less energy than that of a conventional direct mapped cache . Compared with the conventional two - way set ...
122. lappuse
... compared to standard state - of - the - art design techniques . We can exploit this to reduce the system design effort , a single system design can at run - time adapt itself to any timing constraint . Currently , we exploit this ...
... compared to standard state - of - the - art design techniques . We can exploit this to reduce the system design effort , a single system design can at run - time adapt itself to any timing constraint . Currently , we exploit this ...
328. lappuse
... compared the proposed filtering method to the traditional verification framework [ 6 ] of Figure 1 , by developing and executing testbenches on a complex design , a Bluetooth Baseband layer adaptor core , described in SystemC RTL . We ...
... compared the proposed filtering method to the traditional verification framework [ 6 ] of Figure 1 , by developing and executing testbenches on a complex design , a Bluetooth Baseband layer adaptor core , described in SystemC RTL . We ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx