CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 75.
73. lappuse
... communication . Alternatively , it assumes a fixed delay proportional to the communication volume , without taking into consideration subtle effects ( e.g. communication congestion ) which change dynamically throughout tasks execution ...
... communication . Alternatively , it assumes a fixed delay proportional to the communication volume , without taking into consideration subtle effects ( e.g. communication congestion ) which change dynamically throughout tasks execution ...
74. lappuse
Communication Infrastructure Communication Hard Firm Soft 8. REFERENCES Topology Synthesis [ 2 ] Channel Width Sizing Buffer Sizing [ 1 ] A. Jantsch , H. Tenhunen ( Eds . ) . Networks - on - Chip . Kluwer , 2003 . S. Kumar , et . al ...
Communication Infrastructure Communication Hard Firm Soft 8. REFERENCES Topology Synthesis [ 2 ] Channel Width Sizing Buffer Sizing [ 1 ] A. Jantsch , H. Tenhunen ( Eds . ) . Networks - on - Chip . Kluwer , 2003 . S. Kumar , et . al ...
255. lappuse
... communication architectures be- come necessary . In this paper , we extend previous work on automatic communication refinement to support non- traditional , network - oriented architectures beyond a single bus . From an abstract ...
... communication architectures be- come necessary . In this paper , we extend previous work on automatic communication refinement to support non- traditional , network - oriented architectures beyond a single bus . From an abstract ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx