CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 86.
87. lappuse
Increasing On - Chip Memory Space Utilization for Embedded Chip Multiprocessors through Data Compression . Ozcan Ozturk , Mahmut Kandemir , and Mary ... Chip Memory Space Utilization for Embedded Chip Multiprocessors through Data Compression.
Increasing On - Chip Memory Space Utilization for Embedded Chip Multiprocessors through Data Compression . Ozcan Ozturk , Mahmut Kandemir , and Mary ... Chip Memory Space Utilization for Embedded Chip Multiprocessors through Data Compression.
88. lappuse
... chip mem- ory space in a compressed form . When the second request comes , we decompress the data block and forward it to the requester ( an on - chip transfer ) . The advantage of this scheme is that since the data block remains ...
... chip mem- ory space in a compressed form . When the second request comes , we decompress the data block and forward it to the requester ( an on - chip transfer ) . The advantage of this scheme is that since the data block remains ...
90. lappuse
... chip memory space al- located for each processor . As mentioned earlier , although the available on - chip memory space is divided among the processors equally , it is possible to modify our formulation to reflect a non- uniform ...
... chip memory space al- located for each processor . As mentioned earlier , although the available on - chip memory space is divided among the processors equally , it is possible to modify our formulation to reflect a non- uniform ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx