CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 57.
40. lappuse
... cache . Gordon - Ross et al . [ 4 ] extend the analysis to a two - level cache hierarchy , proposing a simultaneous exploration technique for both cache levels that trades off power requirements and performance . Sudarsanam and Malik ...
... cache . Gordon - Ross et al . [ 4 ] extend the analysis to a two - level cache hierarchy , proposing a simultaneous exploration technique for both cache levels that trades off power requirements and performance . Sudarsanam and Malik ...
45. lappuse
... cache sets and utilized. Abstract Caches may consume half of a microprocessor's total power and cache misses incur accessing off - chip memory , which is both time consuming and energy costly . Therefore , minimizing cache power ...
... cache sets and utilized. Abstract Caches may consume half of a microprocessor's total power and cache misses incur accessing off - chip memory , which is both time consuming and energy costly . Therefore , minimizing cache power ...
46. lappuse
that dynamically identified these less accessed cache sets and utilized these cache sets to approximate the global ... cache set access counts for adpcm_enc from Mediabench for an 8 Kbyte cache . 46.
that dynamically identified these less accessed cache sets and utilized these cache sets to approximate the global ... cache set access counts for adpcm_enc from Mediabench for an 8 Kbyte cache . 46.
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx