CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 53.
105. lappuse
... behavior . Runtime DVFS policies must take into consideration program char- acteristics in order to achieve significant energy savings . In this paper , we characterize program behavior and classify programs in terms of the memory ...
... behavior . Runtime DVFS policies must take into consideration program char- acteristics in order to achieve significant energy savings . In this paper , we characterize program behavior and classify programs in terms of the memory ...
322. lappuse
... behavior called phase behavior [ 14 ] . We use the dynamic clustering approach of Sherwood et al . [ 15 ] to track phase behavior through the exe- cution of branches . Our dynamic phase classifier assumes no hardware support , and is ...
... behavior called phase behavior [ 14 ] . We use the dynamic clustering approach of Sherwood et al . [ 15 ] to track phase behavior through the exe- cution of branches . Our dynamic phase classifier assumes no hardware support , and is ...
326. lappuse
... behavior until it converges . Since they can only represent a repetitive region of execution with one converged sample , this means they must find the exact period [ 13 ] of the repeating phase behavior ( if one exists ) and the focus ...
... behavior until it converges . Since they can only represent a repetitive region of execution with one converged sample , this means they must find the exact period [ 13 ] of the repeating phase behavior ( if one exists ) and the focus ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx