CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 60.
44. lappuse
... automated solution that analyzes the code and performs allocation with the aim of optimizing cache efficiency . Our allocation algorithm is being continually evolved . Particular effort is being focused at identifying more accurately ...
... automated solution that analyzes the code and performs allocation with the aim of optimizing cache efficiency . Our allocation algorithm is being continually evolved . Particular effort is being focused at identifying more accurately ...
201. lappuse
... automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays , time ... automate highly repetitive laboratory tasks by replacing cumbersome equipments with miniaturized and integrated ...
... automation approach is expected to relieve biochip users from the burden of manual optimization of bioassays , time ... automate highly repetitive laboratory tasks by replacing cumbersome equipments with miniaturized and integrated ...
243. lappuse
... automated synthesis of arbitrary Java bytecode to hardware . To show the advantages and measure the limited overheads of our approach , we run several accelerated appli- cations ( handwritten and synthesised ) on a real embedded ...
... automated synthesis of arbitrary Java bytecode to hardware . To show the advantages and measure the limited overheads of our approach , we run several accelerated appli- cations ( handwritten and synthesised ) on a real embedded ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx