CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 24.
107. lappuse
... assign- ments for three different categories of programs observed using this bound analysis . 3.1 V / f assignments ... assignment . Program runs the first scaling units at one fre- quency , then switches to the other frequency and runs ...
... assign- ments for three different categories of programs observed using this bound analysis . 3.1 V / f assignments ... assignment . Program runs the first scaling units at one fre- quency , then switches to the other frequency and runs ...
235. lappuse
... assignment . As noted before , it is essential to as- sign accesses to leaves in such a way that concurrent accesses meet only at the root . This can be enforced if a balanced leaf - assignment is made for the accesses within a given C ...
... assignment . As noted before , it is essential to as- sign accesses to leaves in such a way that concurrent accesses meet only at the root . This can be enforced if a balanced leaf - assignment is made for the accesses within a given C ...
275. lappuse
... assignment with maps v : T P and v : L - PUC . Valid configurations resulting from the task allocation problem have ... assignment to processors . The Y , Z , XZs and XZE variables concern link assignment to processors or channels . XZ ...
... assignment with maps v : T P and v : L - PUC . Valid configurations resulting from the task allocation problem have ... assignment to processors . The Y , Z , XZs and XZE variables concern link assignment to processors or channels . XZ ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx