CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 82.
74. lappuse
... architecture for billion transistor era . In Proc . IEEE NorChip Conf , 2000 . [ 3 ] Floorplan W. Dally , B. Towles . Route packets , not wires : On - chip interconnection networks . In Proc . of DAC , June 2001 . [ 4 ] Switching ...
... architecture for billion transistor era . In Proc . IEEE NorChip Conf , 2000 . [ 3 ] Floorplan W. Dally , B. Towles . Route packets , not wires : On - chip interconnection networks . In Proc . of DAC , June 2001 . [ 4 ] Switching ...
131. lappuse
... Architecture Architecture Micro- architecture Circuit Fig . 2. Design approaches for embedded systems microcoded coprocessor architecture , where we have full control for over all the function blocks in the datapath , the communication ...
... Architecture Architecture Micro- architecture Circuit Fig . 2. Design approaches for embedded systems microcoded coprocessor architecture , where we have full control for over all the function blocks in the datapath , the communication ...
291. lappuse
... architecture . A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in the dataflow architecture . In addition to outperforming contemporary embedded ...
... architecture . A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in the dataflow architecture . In addition to outperforming contemporary embedded ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx