CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 83.
22. lappuse
... algorithms for NISC . However , there has been an extensive body of work on scheduling and binding algorithms in the area of high level synthesis , retargetable compilers . Force directed scheduling ( FDS ) [ 1 ] , [ 2 ] is commonly ...
... algorithms for NISC . However , there has been an extensive body of work on scheduling and binding algorithms in the area of high level synthesis , retargetable compilers . Force directed scheduling ( FDS ) [ 1 ] , [ 2 ] is commonly ...
95. lappuse
... algorithms must be identified and / or designed . Fortunately , classical data compression is a mature area ; a number of algorithms exist that can effectively compress data blocks , which tend to be small in size , e.g. , 4KB , 8 KB ...
... algorithms must be identified and / or designed . Fortunately , classical data compression is a mature area ; a number of algorithms exist that can effectively compress data blocks , which tend to be small in size , e.g. , 4KB , 8 KB ...
304. lappuse
... algorithms , an efficient superword construction from data stored in non - adjacent memory ad- dresses . For evaluation purposes we have used a a set of FIR filters of different lengths . From a compiler perspective , this is not one of ...
... algorithms , an efficient superword construction from data stored in non - adjacent memory ad- dresses . For evaluation purposes we have used a a set of FIR filters of different lengths . From a compiler perspective , this is not one of ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx