CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 87.
22. lappuse
... algorithm that compiles the application by performing the scheduling and binding simultaneously . The paper is organized as follows : related works are reviewed in Section 2. In Section 3 we illustrate the algorithm using an example and ...
... algorithm that compiles the application by performing the scheduling and binding simultaneously . The paper is organized as follows : related works are reviewed in Section 2. In Section 3 we illustrate the algorithm using an example and ...
162. lappuse
... algorithm to identify Echo regions and replace them with Echo instructions . This algorithm is based on the well - known LZ77 algorithm [ 20 ] extended for identifying legal Echo regions in binary programs . The algorithm examines each ...
... algorithm to identify Echo regions and replace them with Echo instructions . This algorithm is based on the well - known LZ77 algorithm [ 20 ] extended for identifying legal Echo regions in binary programs . The algorithm examines each ...
312. lappuse
... algorithm to obtain IFG from a basic partition . Second , algorithm to perform itera- tional retiming is presented . 3.2.1 The MDFG Transformation Algorithm The MDFG to IFG transformation algorithm is presented in Algorithm 3.1 . With ...
... algorithm to obtain IFG from a basic partition . Second , algorithm to perform itera- tional retiming is presented . 3.2.1 The MDFG Transformation Algorithm The MDFG to IFG transformation algorithm is presented in Algorithm 3.1 . With ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx