CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 78.
xiv. lappuse
{ Spain nia , Serg in CODES + ISSS 2005 Sponsoring. Additional Reviewers Javed Absar , IMEC , Belgium Yong - Jin Ahn , Seoul National University , Korea James ... Additional Reviewers ( Continued ) Gang - Hee Lee , xiv Additional Reviewers.
{ Spain nia , Serg in CODES + ISSS 2005 Sponsoring. Additional Reviewers Javed Absar , IMEC , Belgium Yong - Jin Ahn , Seoul National University , Korea James ... Additional Reviewers ( Continued ) Gang - Hee Lee , xiv Additional Reviewers.
5. lappuse
... additional leakage power associated with all of the additional latches and re- powering buffers ) . Most designs today have settled on about 8-10 logic levels between latches [ 4 ] , with latches representing about 25 % of all of the ...
... additional leakage power associated with all of the additional latches and re- powering buffers ) . Most designs today have settled on about 8-10 logic levels between latches [ 4 ] , with latches representing about 25 % of all of the ...
9. lappuse
... additional requirements to the convergence processors . Video , in particular , requires high performance to allow the display of movies in real - time . An additional trend for multimedia applications is Java execution . Java provides ...
... additional requirements to the convergence processors . Video , in particular , requires high performance to allow the display of movies in real - time . An additional trend for multimedia applications is Java execution . Java provides ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx