CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 34.
114. lappuse
... adaptation interval . the minimum safe rate Rsafe , this strategy results in energy savings during the low - load periods . If a workload burst starts arriving , the processor frequency is increased accordingly . This is done in a safe ...
... adaptation interval . the minimum safe rate Rsafe , this strategy results in energy savings during the low - load periods . If a workload burst starts arriving , the processor frequency is increased accordingly . This is done in a safe ...
122. lappuse
... adaptation 80 % 70 % 60 % Clock level adaptation Corner - point design 50 % 40 % 30 % 20 % 10 % 0 % 0.754 0.814 0.91 Application level real time constraint 1 Figure 6 : The energy overhead associated to process variability between the ...
... adaptation 80 % 70 % 60 % Clock level adaptation Corner - point design 50 % 40 % 30 % 20 % 10 % 0 % 0.754 0.814 0.91 Application level real time constraint 1 Figure 6 : The energy overhead associated to process variability between the ...
148. lappuse
... Adaptation 1. INTRODUCTION Sensor networks are emerging as a main technology for many applications in national security , health care , envi- ronmental monitoring , infrastructure security , food safety , manufacturing automation and ...
... Adaptation 1. INTRODUCTION Sensor networks are emerging as a main technology for many applications in national security , health care , envi- ronmental monitoring , infrastructure security , food safety , manufacturing automation and ...
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Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx