CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 35.
143. lappuse
... abstraction . In this section we limit the discussion to mainly some of the system level approaches to power estimation . Instruction based power analysis for peripheral cores were first presented in [ 4 ] . This work presented a core ...
... abstraction . In this section we limit the discussion to mainly some of the system level approaches to power estimation . Instruction based power analysis for peripheral cores were first presented in [ 4 ] . This work presented a core ...
164. lappuse
... Abstraction Procedural abstraction [ 3 ] [ 6 ] [ 10 ] converts code common sequences into separate procedures and uses the normal function call / ret mechanism This approach has several disadvantages compared to ET . First , the overlap ...
... Abstraction Procedural abstraction [ 3 ] [ 6 ] [ 10 ] converts code common sequences into separate procedures and uses the normal function call / ret mechanism This approach has several disadvantages compared to ET . First , the overlap ...
249. lappuse
... abstraction gap by implementing a bus interface state machine . The generated processor cores , adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform . Categories and Subject Descriptors : B.8.2 ...
... abstraction gap by implementing a bus interface state machine . The generated processor cores , adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform . Categories and Subject Descriptors : B.8.2 ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx