CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 64.
xii. lappuse
... University / UNICAMP , Brazil Luca Benini , University of Bologna , Italy Joseph Buck , Synopsys , USA Raul Camposano , Synopsys , USA Erwin de Kock , Philips , The Netherlands Sujit Dey , University of California , San Diego , USA Adam ...
... University / UNICAMP , Brazil Luca Benini , University of Bologna , Italy Joseph Buck , Synopsys , USA Raul Camposano , Synopsys , USA Erwin de Kock , Philips , The Netherlands Sujit Dey , University of California , San Diego , USA Adam ...
xiv. lappuse
... University , Japan David Atienza , University Complutense Madrid , Spain Toru Awashima , NEC , Japan Raid Ayoub , University of California , San Diego , USA Rodolfo Azevedo , UNICAMP , Brazil Sudarshan Banerjee , University of ...
... University , Japan David Atienza , University Complutense Madrid , Spain Toru Awashima , NEC , Japan Raid Ayoub , University of California , San Diego , USA Rodolfo Azevedo , UNICAMP , Brazil Sudarshan Banerjee , University of ...
xv. lappuse
... University , Korea Hyung Gyu Lee , Seoul National University , Korea Imyong Lee , Seoul National University , Korea Kyoungwoo Lee , University of California , Irvine , USA Sung - Hyun Lee , Seoul National University , Korea Shih - Wei ...
... University , Korea Hyung Gyu Lee , Seoul National University , Korea Imyong Lee , Seoul National University , Korea Kyoungwoo Lee , University of California , Irvine , USA Sung - Hyun Lee , Seoul National University , Korea Shih - Wei ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx