CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 71.
5. lappuse
... technology has been pipelining . However , as pipelines have become deeper and the number of logic levels between latches has decreased , the power and device count have increased dramatically . This is due to the increased number of ...
... technology has been pipelining . However , as pipelines have become deeper and the number of logic levels between latches has decreased , the power and device count have increased dramatically . This is due to the increased number of ...
161. lappuse
... technology and illustrates how it can reduce code size . Section 5 describes ET algorithms . Section 6 proposes new IA32 Echo instructions and presents the evaluation results . Section 7 discusses future work . Section 8 concludes the ...
... technology and illustrates how it can reduce code size . Section 5 describes ET algorithms . Section 6 proposes new IA32 Echo instructions and presents the evaluation results . Section 7 discusses future work . Section 8 concludes the ...
180. lappuse
... technology is usually called XIP [ 3 ] . Currently , the XIP technology is supported only by a single processor . Therefore , we developed a new XIP technology for the FIDES platform , called as XIP kernels , which is improved from a ...
... technology is usually called XIP [ 3 ] . Currently , the XIP technology is supported only by a single processor . Therefore , we developed a new XIP technology for the FIDES platform , called as XIP kernels , which is improved from a ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx