CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 7.
161. lappuse
... Echo technology and illustrates how it can reduce code size . Section 5 describes ET algorithms . Section 6 proposes new IA32 Echo instructions and presents the evaluation results ... Echo target and the Echo region may have not been. 161.
... Echo technology and illustrates how it can reduce code size . Section 5 describes ET algorithms . Section 6 proposes new IA32 Echo instructions and presents the evaluation results ... Echo target and the Echo region may have not been. 161.
162. lappuse
... Echo region will be replaced by an Echo instruction and the branch target will no longer exist afterward . Furthermore , internal control flow inside an Echo region , such as looping or branching to internal blocks , makes the semantics ...
... Echo region will be replaced by an Echo instruction and the branch target will no longer exist afterward . Furthermore , internal control flow inside an Echo region , such as looping or branching to internal blocks , makes the semantics ...
163. lappuse
Echo target and the Echo region may have not been finalized yet . The size of the Echo instruction depends on the offset from the Echo region to the Echo target , which may be unknown when a non - terminal or an interior node is ...
Echo target and the Echo region may have not been finalized yet . The size of the Echo instruction depends on the offset from the Echo region to the Echo target , which may be unknown when a non - terminal or an interior node is ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx