CODES+ISSSACM Press, 2005 |
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1.–3. rezultāts no 74.
32. lappuse
... Computer Aided Design , 1992 , 292-299 . [ 3 ] Vijay Kumar , V. , Lach , J. Designing , scheduling , and allocating flexible arithmetic components . In Proceedings of the International Conference on Field Programmable Logic and ...
... Computer Aided Design , 1992 , 292-299 . [ 3 ] Vijay Kumar , V. , Lach , J. Designing , scheduling , and allocating flexible arithmetic components . In Proceedings of the International Conference on Field Programmable Logic and ...
110. lappuse
... Computer Sciences Dept. , July 1996 . [ 6 ] K. Choi , R. Soma , and M. Pedram . Fine - grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off - chip access to on - chip ...
... Computer Sciences Dept. , July 1996 . [ 6 ] K. Choi , R. Soma , and M. Pedram . Fine - grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off - chip access to on - chip ...
200. lappuse
... Computer - Aided Design 22 ( 2 ) : 155-170 , 2003 [ 67 ] A. Oliveira , J. R. Phillips , J. Afonso , and L. M. Silveira . Analog macromodeling using kernel methods . In International Conference on Computer Aided - Design , Santa Clara ...
... Computer - Aided Design 22 ( 2 ) : 155-170 , 2003 [ 67 ] A. Oliveira , J. R. Phillips , J. Afonso , and L. M. Silveira . Analog macromodeling using kernel methods . In International Conference on Computer Aided - Design , Santa Clara ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx