Multiprocessor Systems-on-ChipsAhmed Jerraya, Wayne Wolf Morgan Kaufmann, 2005 - 581 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 84.
i. lappuse
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vi. lappuse
... Methodologies 11 Hardware Architectures 13 1.7 Software 14 1.7.1 1.7.2 1.7.3 1.8 Programmer's Viewpoint 14 Software architecture and design reuse viewpoint 15 Optimization Viewpoint 16 The Rest of the Book 18 vi xix 1 viii PART I ...
... Methodologies 11 Hardware Architectures 13 1.7 Software 14 1.7.1 1.7.2 1.7.3 1.8 Programmer's Viewpoint 14 Software architecture and design reuse viewpoint 15 Optimization Viewpoint 16 The Rest of the Book 18 vi xix 1 viii PART I ...
xii. lappuse
... Methodology 225 8.2.2 Performance Modeling with Architecture Services 227 Mechanics of Architecture Services 8.2.3 229 8.2.4 Architecture Topology Binds Services 230 Communication Patterns 231 Modeling of Dataflow Networks 233 8.2.5 8.3 ...
... Methodology 225 8.2.2 Performance Modeling with Architecture Services 227 Mechanics of Architecture Services 8.2.3 229 8.2.4 Architecture Topology Binds Services 230 Communication Patterns 231 Modeling of Dataflow Networks 233 8.2.5 8.3 ...
xiv. lappuse
... Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 11.5.4 Platform Simulation Environment 326 3D Rendering QoS Application 327 11.6 11.7 11.7.1 11.8 Experimental Results 329 Gray ...
... Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 11.5.4 Platform Simulation Environment 326 3D Rendering QoS Application 327 11.6 11.7 11.7.1 11.8 Experimental Results 329 Gray ...
xv. lappuse
... METHODOLOGY AND APPLICATIONS 13 Component-Based Design for Multiprocessor Systems-on-Chip Wander O. Cesário and Ahmed A. Jerraya 13.1 From ASIC to System and Network on Chip 357 Applications for MPSoC 358 13.1.1 13.2 Basics for MPSoC ...
... METHODOLOGY AND APPLICATIONS 13 Component-Based Design for Multiprocessor Systems-on-Chip Wander O. Cesário and Ahmed A. Jerraya 13.1 From ASIC to System and Network on Chip 357 Applications for MPSoC 358 13.1.1 13.2 Basics for MPSoC ...
Saturs
Chapter 1 The What Why and How of MPSoCs | 1 |
Hardware | 19 |
SOFTWARE | 249 |
METHODOLOGY AND APPLICATIONS | 355 |
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa