Multiprocessor Systems-on-ChipsModern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.5. rezultāts no 5.
302. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
472. lappuse
However, Ptolemy, SystemC, and SpecC lack features that are necessary to
orthogonalize functionality and architecture, such as the mapping between
functional and architectural networks, or between different refinement levels.
Ptolemy only ...
However, Ptolemy, SystemC, and SpecC lack features that are necessary to
orthogonalize functionality and architecture, such as the mapping between
functional and architectural networks, or between different refinement levels.
Ptolemy only ...
556. lappuse
Atvainojiet, šīs lappuses saturs ir ierobežots..
Atvainojiet, šīs lappuses saturs ir ierobežots..
577. lappuse
See Register-transfer-level (RTL) design RTOS,10 RTOS model, abstract,
SystemC-based, 290292, 291f basic concepts of, 286289 introduction to, 283
285, 284f methodology of, 285 multiprocessor systems, 303310 terminology
related ...
See Register-transfer-level (RTL) design RTOS,10 RTOS model, abstract,
SystemC-based, 290292, 291f basic concepts of, 286289 introduction to, 283
285, 284f methodology of, 285 multiprocessor systems, 303310 terminology
related ...
579. lappuse
... 6568 Synchronization failures, 54 Synchronization model, of SystemC-based
abstract RTOS model, 300302 Synchronous, defined, 509 Synchronous
dataflow (SDF), 440, 446t, 447 Synchronous DRAM, 259260 Synthesis, in
Metropolis, ...
... 6568 Synchronization failures, 54 Synchronization model, of SystemC-based
abstract RTOS model, 300302 Synchronous, defined, 509 Synchronous
dataflow (SDF), 440, 446t, 447 Synchronous DRAM, 259260 Synthesis, in
Metropolis, ...
Lietotāju komentāri - Rakstīt atsauksmi
Ierastajās vietās neesam atraduši nevienu atsauksmi.
Saturs
Chapter 1 The What Why and How of MPSoCs | 1 |
Hardware | 19 |
SOFTWARE | 249 |
METHODOLOGY AND APPLICATIONS | 355 |
Glossary | 497 |
References | 513 |
Contributor Biographies | 557 |
567 | |
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstract algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit clock communication architecture communication protocols compiler complex components Computer-Aided Design configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory MoCs modules MPSoC multimedia multiple multiprocessor nodes number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform priority Proc resource RISC RTOS run-time scheduling shared signal simulation SoC design specific static subsystem superscalar switching Symposium synchronization system design system-on-chip SystemC target task techniques tion topology Ubicom VLIW VLSI voltage WCET wrapper Xtensa