Source Code Optimization Techniques for Data Flow Dominated Embedded Software

Pirmais vāks
Springer Science & Business Media, 2004. gada 20. dec. - 226 lappuses
This book focuses on source-to-source code transformations that remove addressing-related overhead present in most multimedia or signal processing application programs. This approach is complementary to existing compiler technology. What is particularly attractive about the transformation flow pre sented here is that its behavior is nearly independent of the target processor platform and the underlying compiler. Hence, the different source code trans formations developed here lead to impressive performance improvements on most existing processor architecture styles, ranging from RISCs like ARM7 or MIPS over Superscalars like Intel-Pentium, PowerPC, DEC-Alpha, Sun and HP, to VLIW DSPs like TI C6x and Philips TriMedia. The source code did not have to be modified between processors to obtain these results. Apart from the performance improvements, the estimated energy is also significantly reduced for a given application run. These results were not obtained for academic codes but for realistic and rep resentative applications, all selected from the multimedia domain. That shows the industrial relevance and importance of this research. At the same time, the scientific novelty and quality of the contributions have lead to several excellent papers that have been published in internationally renowned conferences like e. g. DATE. This book is hence of interest for academic researchers, both because of the overall description of the methodology and related work context and for the detailed descriptions of the compilation techniques and algorithms.
 

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Atlasītās lappuses

Saturs

INTRODUCTION
1
11 Why Source Code Optimization?
3
111 Abstraction Levels of Code Optimization
4
112 Survey of the traditional Code Optimization Process
5
113 Scopes for Code Optimization
8
12 Target Application Domain
10
13 Goals and Contributions
11
14 Outline of the Book
12
551 Standalone Loop Nest Splitting
101
5511 Pipeline and Cache Performance
102
5512 Execution Times and Code Sizes
107
5513 Energy Consumption
109
552 Combined Data Partitioning and Loop Nest Splitting for energyefficient Scratchpad Utilization
110
5521 Execution Times and Code Sizes
111
5522 Energy Consumption
113
56 Summary
116

EXISTING CODE OPTIMIZATION TECHNIQUES
15
21 Description Optimization
16
22 Algorithm Selection
17
24 Processorindependent Source Code Optimizations
19
25 Processorspecific Source Code Optimizations
20
26 Compiler Optimizations
21
262 Code Generation for embedded Processors
23
FUNDAMENTAL CONCEPTS FOR OPTIMIZATION AND EVALUATION
25
32 Optimization using Genetic Algorithms
29
33 Benchmarking Methodology
34
332 Compilation for Runtime and Code Size Measurement
35
333 Estimation of Energy Dissipation
37
34 Summary
38
INTERMEDIATE REPRESENTATIONS AND THEIR SUITABILITY FOR SOURCE CODE OPTIMIZATION
41
41 Lowlevel Intermediate Representations
42
412 Trimaran ELCOR IR
43
42 Mediumlevel Intermediate Representations
44
422 IRCLANCE
45
43 Highlevel Intermediate Representations
47
432 IMPACT
48
45 Summary
51
LOOP NEST SPLITTING
53
511 Control Flow Overhead in Data Flow dominated Software
54
512 Control Flow Overhead caused by Data Partitioning
55
513 Splitting of Loop Nests for Control Flow Optimization
57
52 Related Work
60
53 Analysis and Optimization Techniques for Loop Nest Splitting
62
531 Preliminaries
64
532 Condition Satisfiability
67
533 Condition Optimization
69
5331 Chromosomal Representation
70
5332 Fitness Function
73
5333 Polytope Generation
79
534 Global Search Space Construction
80
535 Global Search Space Exploration
82
5351 Chromosomal Representation
83
5352 Fitness Function
84
536 Source Code Transformation
90
5362 Loop Nest Duplication
92
54 Extensions for Loops with nonconstant Bounds
94
55 Experimental Results
100
ADVANCED CODE HOISTING
119
62 Related Work
124
63 Analysis Techniques for Advanced Code Hoisting
129
631 Common Subexpression Identification
130
6312 Computation of Live Ranges of Expressions
132
632 Determination of the outermost Loop for a CSE
139
633 Computation of Execution Frequencies using Polytope Models
141
64 Experimental Results
154
642 Execution Times and Code Sizes
158
643 Energy Consumption
160
65 Summary
161
RING BUFFER REPLACEMENT
163
71 Motivation
164
72 Optimization Steps
169
721 Ring Buffer Scalarization
170
722 Loop Unrolling for Ring Buffers
171
73 Experimental Results
173
732 Execution Times and Code Sizes
176
733 Energy Consumption
178
74 Summary
179
SUMMARY AND CONCLUSIONS
181
82 Future Work
184
Experimental Comparison of SUIF and IRCLANCE
189
Benchmarking Data for Loop Nest Splitting
191
B12 Sun UltraSPARC III
193
B13 MIPS R10000
194
B2 Execution Times and Code Sizes
195
B3 Energy Consumption of an ARM7TDMI Core
197
B4 Combined Data Partitioning and Loop Nest Splitting
198
B42 Energy Consumption
199
Benchmarking Data for Advanced Code Hoisting
201
C12 Sun UltraSPARC III
202
C13 MIPS R10000
203
C3 Energy Consumption of an ARM7TDMI Core
205
Benchmarking Data for Ring Buffer Replacement
207
D12 Sun UltraSPARC III
208
D3 Energy Consumption of an ARM7TDMI Core
209
References
211
About the Authors
221
Index
223
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Populāri fragmenti

218. lappuse - ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES), Vancouver, Canada, June 2000.
218. lappuse - ... [23] Texas Instruments, www.ti.com/sc/c6x, 2000. [24] V. Tiwari, S. Malik, and A. Wolfe. Power Analysis of Embedded Software: A First Step towards Software Power Minimization. In Transactions on VLSI Systems. IEEE, December 1994. [25] G.-R. Uh, Y. Wang, D. Whalley, S. Jinturkar, C. Burns, and V. Cao. Effective Exploitation of a Zero Overhead Loop Buffer. In Proceedings of Workshop on Languages, Compilers, and Tools for Embedded Systems, pages 10-19, May 1999.

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