 | Marvin Zelkowitz, Ali R. Hurson - 2005 - 312 lapas
...and modeling challenges for next-generation microprocessors", IEEE Micro (December 2000) 26-44. ( 10] Brooks D., Tiwari V., Martonosi M., "Wattch: a framework...architectural-level power analysis and optimizations", in: Proceedings of the 27th International Symposium on Computer Architecture (ISCA). June 2000. [11| Burger... | |
 | Marvin Zelkowitz - 2005 - 312 lapas
...and modeling challenges for next-generation microprocessors", IEEE Micro (December 2000) 26-44. [10] Brooks D., Tiwari V., Martonosi M., "Wattch: a framework...architectural-level power analysis and optimizations", in: Proceedings of the 27th International Symposium on Computer Architecture (ISCA), June 2000. [11] Burger... | |
 | Timo D. H?m?l?inen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis - 2005 - 489 lapas
...Austin, TM: The simplescalar tool set, version 2.0. SIGARCH Comput. Archit. News 25 (1997) 13-25 9. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework...architectural-level power analysis and optimizations. In: Proc. of the Internat. symposium on Computer architecture. (2000) 83-94 10. Sherwood, T., Perelman,... | |
 | Srinivas Aluru, Manish Parashar, Ramamurthy Badrinath, Viktor K. Prasanna - 2007 - 687 lapas
...leakage for architects. Technical Report CS-2003-05. Dept. of CS, University of Virginia (2003) [13] Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework...architectural-level power analysis and optimizations. In: Proc. 27th IEEE/ ACM International Symposium on Computer Architecture, pp. 83-94 (2000) Self -optimization... | |
 | Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer - 2007 - 307 lapas
...instruction scheduling logic. In: Proceedings of International Symposium On Microarchitecture. (2001) 13. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework...architectural-level power analysis and optimizations. In: Proceedings of the International Symposium on Computer Architecture. (2000) 83-94 15. Bai, R., Sylvester,... | |
 | Tat-Jen Cham, Jianfei Cai, Chitra Dorai, Deepu Rajan, Tat-Seng Chua, Liang-Tien Chia - 2006 - 756 lapas
...Set. Computer Architecture News (1997) See also http://www.simplescalar.com for more information. 9. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework...architectural-level power analysis and optimizations. In: Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA-27). (2000) 83-94... | |
 | Nadine Azemard - 2007 - 595 lapas
...Grunwald, D.: The SimpleScalar-Arm power modeling project, http: //www. eecs .umich.edu/~panalyzer/ 4. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework...architectural-level power analysis and optimizations. In: Proceedings of the 27th Annual International Symposium on Computer Architecture (June 2000) 5. Contreras,... | |
 | Carla Schlatter Ellis - 2007 - 98 lapas
...Operating System (EW9), Kolding, Denmark, September 17-20, 2000, pp. 37-42. Brooks, D., Tiwari, V., and Martonosi, M., "Wattch: a framework for architectural-level power analysis and optimizations," in 27th Annual Int. Symp. on Computer Architecture (ISCA),]\m& 2000, pp. 83-94. Carter, C., Kravets, R.,... | |
 | Luc Bougé, Franck Cappello, Jack J. Dongarra, Thomas Hérault - 2008 - 247 lapas
...chip-multiprocessor caches. In: Proc. of the 37th MICRO, pp. 319-330. IEEE Computer Society, Los Alamitos (2004) 3. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework...ArchitecturalLevel Power Analysis and Optimizations. In: Proc. of the 27th Int. Symp. Comp. Arch., pp. 83-94. IEEE Computer Society, Los Alamitos (2000) 4.... | |
 | Jesus Labarta - 2008 - 536 lapas
...fine grain parallel processing on single chip multiprocessors. Trans, of IPSJ 40(5) (May 1999) 23. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework...architectural-level power analysis and optimizations. In: Proc. of the 27th ISCA (June 2000) 24. Kawaguchi, H., Shin, Y, Sakurai, T.: uITRON-LP: Power-conscious... | |
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Brooks D., Tiwari V., Martonosi M., "Wattch: a framework for architectural-level power analysis and optimizations", in: Proceedings of the 27th International Symposium on Computer Architecture (ISCA). 