Advances in Computers: Architectural AdvancesMarvin Zelkowitz Elsevier, 2011. gada 21. sept. - 342 lappuses The series covers new developments in computer technology. Most chapters present an overview of a current subfield within computers, with many citations, and often include new developments in the field by the authors of the individual chapters. Topics include hardware, software, theoretical underpinnings of computing, and novel applications of computers. This current volume emphasizes architectural advances and includes five chapters on hardware development, games for mobile devices such as cell phones, and open source software development. The book series is a valuable addition to university courses that emphasize the topics under discussion in that particular volume as well as belonging on the bookshelf of industrial practitioners who need to implement many of the technologies that are described.
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1.–5. rezultāts no 66.
... Sharing of Resources . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.5. A Unified Conjoined-Core ... Shared Bus Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3. P2P Links ...
... sharing large, overprovisioned structures. Intelligently scheduling accesses to the shared resources enables conjoined-core architectures to achieve significantly higher efficiency (throughput/area) than their “multi-core oblivious ...
... shared a 128 KB level-2 cache. Hydra was focused not only on providing hardware parallelism for throughput-oriented applications, but also on providing high single-thread performance for applications that can be parallelized into ...
... shared triply-banked 8-way set-associative L2 cache. The connection was through a high-bandwidth crossbar switch (called crossbarinterface unit). Four Power4 chips could be connected together within a multi-chip module and made to ...
... shared L2 cache interactions. However, determining this configuration is only possible by running all possible combinations. Instead, as a simplifying assumption, our scheduling policy assumes no knowledge of L2 interactions (only for ...
Saturs
Chapter 2 Designing Computational Clusters for Performance and Power | 89 |
Chapter 3 CompilerAssisted Leakage Energy Reduction for Cache Memories | 155 |
Challenges and Opportunities | 191 |
Recent Research Results and Methods | 243 |
Author Index | 297 |
Subject Index | 307 |
Contents of Volumes in this Series | 319 |
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Advances in Computers: Architectural Advances Marvin Zelkowitz, Ph.D., MS, BS. Priekšskatījums nav pieejams - 2007 |
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