Advances in Computers: Architectural AdvancesMarvin Zelkowitz Elsevier, 2011. gada 21. sept. - 342 lappuses The series covers new developments in computer technology. Most chapters present an overview of a current subfield within computers, with many citations, and often include new developments in the field by the authors of the individual chapters. Topics include hardware, software, theoretical underpinnings of computing, and novel applications of computers. This current volume emphasizes architectural advances and includes five chapters on hardware development, games for mobile devices such as cell phones, and open source software development. The book series is a valuable addition to university courses that emphasize the topics under discussion in that particular volume as well as belonging on the bookshelf of industrial practitioners who need to implement many of the technologies that are described.
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No grāmatas satura
1.–5. rezultāts no 84.
... . . . . . . . . . . . . . . . . . . . . . . . . . . 149 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 v 1. 2. 3. 4. Compiler-Assisted Leakage Energy Reduction for Cache Contents.
... Reduction for Cache Memories Wei Zhang 1. Introduction ... Reduction . . . . . . 170 5. Evaluation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6. Conclusion ...
... Reduction for Cache Memories,” Wei Zhang considers the same heat problem discussed in Chapter 2, but addresses the issue of cache memories. Since processor speeds (on the order of 109 cycles per second) is much faster than the speeds of ...
... reduce processor power dissipation. That section also discusses methodologies for holistic, ground-up design of multi-core architecture and demonstrates their benefits over processors designed using off-the-shelf components. Section 4 ...
... reduction in the size of register files, instruction queues, the reorder buffer, and renaming tables to account for the single-threaded EV8-. For this, we use detailed models of the register bit equivalents (rbe) [73] THE ARCHITECTURE ...
Saturs
Chapter 2 Designing Computational Clusters for Performance and Power | 89 |
Chapter 3 CompilerAssisted Leakage Energy Reduction for Cache Memories | 155 |
Challenges and Opportunities | 191 |
Recent Research Results and Methods | 243 |
Author Index | 297 |
Subject Index | 307 |
Contents of Volumes in this Series | 319 |
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Advances in Computers: Architectural Advances Marvin Zelkowitz, Ph.D., MS, BS. Priekšskatījums nav pieejams - 2007 |
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