Advances in Computers: Architectural AdvancesMarvin Zelkowitz Elsevier, 2011. gada 21. sept. - 342 lappuses The series covers new developments in computer technology. Most chapters present an overview of a current subfield within computers, with many citations, and often include new developments in the field by the authors of the individual chapters. Topics include hardware, software, theoretical underpinnings of computing, and novel applications of computers. This current volume emphasizes architectural advances and includes five chapters on hardware development, games for mobile devices such as cell phones, and open source software development. The book series is a valuable addition to university courses that emphasize the topics under discussion in that particular volume as well as belonging on the bookshelf of industrial practitioners who need to implement many of the technologies that are described.
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1.–5. rezultāts no 49.
... implemented in 0.5 micron technology [17]. Alpha 21264 (also called, and henceforth referred to as, EV6) is an out-of-order processor that was originally implemented in 0.35 micron technology [18]. If we assume both the processors to be ...
... implemented, but an implementation of Hydra (0.25 micron technology) was estimated to take up 88 mm2 of area. One of the earliest commercial multi-core proposals, Piranha [23] (description published in 2000) was an 8-way chip ...
... implementation of Power4 (in 0.13 micron technology) consisted of 184 million transistors and took up 267 mm2 in die-area. IBM also later came up with successors to Power4, like Power5 [50] and Power6. However, IBM's most ambitious ...
... implemented in 0.10 micron technology and are clocked at 2.1 GHz. In addition to the individual L1 caches, all the cores share an on-chip 4 MB, 4-way set-associative, 16-way L2 cache. The cache line size is 128 bytes. Each bank of the ...
... some combination of energy and performance). In addition, the demands of a single. FIG. 3. Benefits of dynamic scheduling. FIG. 4. Relative sizes of the Alpha cores when implemented. THE ARCHITECTURE OF EFFICIENT MULTI-CORE PROCESSORS 19.
Saturs
Chapter 2 Designing Computational Clusters for Performance and Power | 89 |
Chapter 3 CompilerAssisted Leakage Energy Reduction for Cache Memories | 155 |
Challenges and Opportunities | 191 |
Recent Research Results and Methods | 243 |
Author Index | 297 |
Subject Index | 307 |
Contents of Volumes in this Series | 319 |
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Advances in Computers: Architectural Advances Marvin Zelkowitz, Ph.D., MS, BS. Priekšskatījums nav pieejams - 2007 |
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