Advances in Computers: Architectural AdvancesMarvin Zelkowitz Elsevier, 2011. gada 21. sept. - 342 lappuses The series covers new developments in computer technology. Most chapters present an overview of a current subfield within computers, with many citations, and often include new developments in the field by the authors of the individual chapters. Topics include hardware, software, theoretical underpinnings of computing, and novel applications of computers. This current volume emphasizes architectural advances and includes five chapters on hardware development, games for mobile devices such as cell phones, and open source software development. The book series is a valuable addition to university courses that emphasize the topics under discussion in that particular volume as well as belonging on the bookshelf of industrial practitioners who need to implement many of the technologies that are described.
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1.–5. rezultāts no 19.
... pattern. Each tile consists of communication routers, one scalar core, an FPU (floating-point unit), a 32 KB DCache, and a software-managed 96 KB ICache. Tiles are sized such that the latency 8 R. KUMAR AND D.M. TULLSEN.
... D-Cache 8 KB, DM 64 KB, 2-way Branch Pred. 2K-gshare hybrid 2-level Number of MSHRs 4 8 Number of threads 1 1 Area (in mm2) 5.06 24.5 over a wide range of available thread-level parallelism. It would THE ARCHITECTURE OF EFFICIENT MULTI ...
... D-Cache 8 KB, DM 8 KB, DM 64 KB, 2-way 64 KB, 4-way Branch Pred. 2 KB,1-bit 2 K-gshare hybrid 2-level hybrid 2-level (2X EV6 size) Number of MSHRs 2 4 8 16 TABLE III POWER AND AREA STATISTICS OF THE ALPHA CORES 22 R. KUMAR AND D.M. TULLSEN.
... D-Cache 8 KB-DM, 16 KB 2-way, 32 KB 4-way, 64 KB 4-way dual ported FP-IntMul-ALU units 1-1-2, 2-2-4 IntQ-fpQ (OOO) 32-16, 64-32 Int-FP PhysReg-ROB (OOO) 64-64-32, 128-128-64 L2 Cache 1 MB/core, 4-way, 12 cycle access Memory Channel 533 ...
... DCache, one scalar OOO core with 32 KB ICache, 16 KB DCache and double the functional units, and one scalar OOO core with 64 KB ICache and 32 KB DCache. The three core types cover the spectrum of application requirements better and ...
Saturs
Chapter 2 Designing Computational Clusters for Performance and Power | 89 |
Chapter 3 CompilerAssisted Leakage Energy Reduction for Cache Memories | 155 |
Challenges and Opportunities | 191 |
Recent Research Results and Methods | 243 |
Author Index | 297 |
Subject Index | 307 |
Contents of Volumes in this Series | 319 |
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Advances in Computers: Architectural Advances Marvin Zelkowitz, Ph.D., MS, BS. Priekšskatījums nav pieejams - 2007 |
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