Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 56.
... tion. Defects and faults in ICs, caused either by manufacturing imperfections or by designer errors, can cause everything from satellite and rocket malfunctions, to glitches and failures in consumer applications. One well-known case is ...
... tion engineers are forced to verify narrower sets of properties. 2 Two lessons that engineers can learn are well understood by homemakers when providing for their families: quality costs, but it pays over time. Fabrication Specification ...
... tion, emulation and formal verification. Synthesizing assertion-checking circuits is an effective way of allowing assertions to be used in the verification, silicon debug- ging and on-line monitoring steps in the flow in Figure 1.1. The ...
... tion of assertions as used in traditional simulators, and can even extend into formal verification by allowing certain types of properties to be used in model checkers that do not support PSL and SVA. The techniques used in developing ...
... tion [107]. Chapters 5 and 6 introduce the core notions to generating assertion checkers in this book. Chapter 5 introduces the automata framework used to symbolically repre- sent assertions. Other important functions that are not ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |