Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 51.
... Statements 81 5 Automata for Assertion Checkers 83 5.1 Introduction and Overview . 83 5.2 5.2.4 Complementation of Automata Automaton Framework .. 5.2.2 Determinization of Automata 5.2.3 Minimization of Automata 5.3 Generating Circuit ...
... Statements 225 9.3 Experimental Results for SVA Checkers 229 9.3.1 Non - synthetic Assertions . 229 9.3.2 Benchmarking Sequences and Properties 235 9.3.3 Using SVA Checkers with Formal Verification Tools . . 240 10 Conclusions and ...
... statements built on temporal logic that are added to a design under verification in order to specify how the circuit should behave. Assertions can (and should) be added before the verification step, and should be part of the design ...
... statement like the preceding one makes no assumptions on the state of the Booleans in other clock cycles , and in the previous example , a can be true or false in the clock cycle where b was mentioned , and b can be true or false in the ...
... statements can also be used as primitives in contract-based programming [128] and related para- digms. By now, assertions are widely used in software development. According to an- other great computer scientist who has extensively dealt ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |