Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 78.
... opens up the way for their use in severely needed post-fabrication debugging, as increasingly the ICs are discovered to be incorrect after manufacturing. The impact of this work on post-fabrication debugging will clearly show in ix.
... show in the years to come, as companies start adopting assertions in debugging. This book is intended for anyone wanting to use assertions more effectively as means to improve the quality of their designs, and for those wanting to know ...
... shows a summary of the main engineering tasks leading to a finished in- tegrated circuit. Assertions should ideally be used in the specification stage to allow the formal documentation of requirements. More details on various uses of ...
... show that the MBAC checker gen- erator produces smaller and faster circuits that offer the correct assertion behavior while supporting all simple subset operators. Chapter 9 is devoted to checker generation for SystemVerilog assertions ...
... shows that in 2005, over 20% of total design resources are spent on post-fabrication validation [144], thus asser- tions can potentially have a large financial impact to help decrease project costs. Looking from this perspective, it is ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |