Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 48.
... semantics for these languages have been published. Furthermore, numerous books that present assertion patterns, applied examples, and methodology suggestions targeted at de- signers and verification engineers have hit the market ...
... semantics and rewrite rules • Chapter 7: Debug enhancements for checkers, checker use in post-fabrication debugging, self test and on-line monitoring • Chapter 8: Experimental results for PSL checkers, benchmarking of real and syn ...
... semantics of operators can (and should) complement their reading with such documents (Appendix B in [108] and Appendix E in [107]). Although the checkers generated in this work apply to a variety of scenarios, including formal ...
... Semantics . Basic Techniques Behind Assertion Checkers . 3.1 Background 3.1.1 Regular Expressions and Classical Automata 3.1.2 Automata in Model Checking . . . . 7 9 13 13 16 20 24 27 28 33 37 37 38 44 3.2 Modular Approach to Checker ...
... semantics for hardware as- sertion checkers. Although a few algorithms and rewrite rules follow from classical automata theory and the PSL/SVA specifications respectively, all are implemented 6 1 Introduction Book Objectives.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |