Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 40.
... checkers for modern assertion languages. The book's main topics are organized as ... checking, post-fabrication debugging, formal and dynamic verification ... model checkers that do not support assertion languages, as shown in Chapter ...
... Verification . 2.7 Supported Simulation and Emulation Semantics . Basic Techniques Behind Assertion Checkers . 3.1 Background 3.1.1 Regular Expressions and Classical Automata 3.1.2 Automata in Model Checking . . . . 7 9 13 13 16 20 24 ...
... checking circuits is an effective way of allowing assertions to be used in ... model checkers and theorem provers in static verification. When large ... Checker generator for hardware verification. 4 1 Introduction.
... verification by allowing certain types of properties to be used in model checkers that do not support PSL and SVA. The techniques used in developing the checker generator can further be applied to areas as diverse as hardware ...
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring Marc Boulé, Zeljko Zilic. of related research on assertion checkers. The use of automata in formal verification, more specifically in model checking ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |