Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 74.
... Logic Synthesis course ( ECSE 530 ) . Valuable feedback was ob- tained from ( alphabetically ) : Ivan Bilicki , Alexandu Ciobanu , Michael Dang'ana , Sandrine Filion - Côté , Yu Pang , Sunyoung Park , Sayeeda Sultana , Jason Tong ...
... Logic CPU Central Processing Unit CUT Circuit Under Test DFA Deterministic Finite Automaton DFF D - type Flip - Flop DUV Design Under Verification EDA EOE FF FL FPGA HDL IC IEEE IP LTL LUT Lookup Table NFA Electronic Design Automation ...
... logic bug in a Boolean function is an example of a design fault, whereas stuck-at-value faults and short circuits are examples of fabri- cation faults. When a correct circuit subsequently becomes faulty under unexpected conditions or ...
... logic that are added to a design under verification in order to specify how the circuit should behave. Assertions can (and should) be added before the verification step, and should be part of the design process as well. Figure 1.1 shows ...
... logic gates is introduced in Section 7.3 for imple- menting a more efficient form of the eventually! operator, when compared to the rewrite rule developed in Chapter 6. The results of all challenges are assessed empirically in Chapter 8 ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |