Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 70.
... implementing checkers for PSL in their own research tools will find Chapters 5 and 6 of particular interest, while those dealing with SVA can focus more on Chapter 9. In the case of SVA however, many topics and algorithms from the PSL ...
... implemented in a circuit form, and should be fast, to allow high clock speeds; and (2) that they continually report errors in real time as the design is executed, as opposed to a static result at the end of execution. Many design ...
... implementation verification tasks on the road to obtaining a working design. Essentially, every transformation or refinement step requires its verification. For instance, translation of high-level architectural descriptions into more ...
... implementation in circuit form. Generating resource-efficient assertion-checking circuits is of primary impor- tance when assertion-based verification is to be used in hardware emulation, post- fabrication silicon debugging and on-line ...
... implementations. In one example, a checker that is three or- ders of magnitude smaller in terms of code size was ... implemented in hardware. Many design choices and optimizations are performed with the underlying goal of reducing the ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |