Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 54.
... formal verification, emulation, post-silicon debug- ging, and hardware runtime monitoring can use these checkers. With the emergence of assertion language and library standards – such as the IEEE SystemVerilog As- sertions (SVA), the ...
... formal and dynamic verification • Chapter 3: Background on regular expressions, finite automata and the different approaches to generating checkers • Chapter 4: PSL and SVA assertions languages • Chapter 5: Finite automata theory and ...
... formal verification, the primary context that is targeted is dynamic veri- fication (ex: simulation, emulation). The checkers are designed with the goals that: (1) they should require few hardware resources when implemented in a circuit ...
... Formal Verification Tools . . 240 10 Conclusions and Future Work 251 10.1 Conclusion . . 251 10.2 Future Work .. 253 10.2.1 Optimizations and Improvements 253 10.2.2 Checkers and Debugging . 254 10.2.3 Assertion Language Compilation 255 ...
... formal documentation language, free of the am- biguities inherent to natural language specifications. In another view, assertions can be seen as an executable specification [108], or a computable specification, when interpreted by ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |