Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 79.
... Failure - Matching Sequences 200 8.6.4 Properties ..203 9 Checkers for System Verilog Assertions 207 9.1 Introduction and Overview . . . 9.2 Checker Generation for SystemVerilog Assertions 207 207 9.2.1 Automata Construction for ...
... failures in consumer applications. One well-known case is the floating- point error found on early models of the Pentium processor by Intel. This “bug”, known as the FDIV bug was not a fabrication or manufacturing defect, but rather a ...
... Failures of various types that escape to the products then become a liability in the product chain, which is a lesson that the engineers and their managers learn the hard way over and over again [58]2. The measures for quality ...
... failure than any other tech- nique for pass/fail checking. This becomes even more relevant in the post-silicon, or post-fabrication stage debugging. Due to the complexity, and uncertainties of modern processes, the percentage of ICs ...
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Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |