Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 92.
... Examples of types of faults that can be present in digital circuits are: design faults, fabrication faults and faults that arise during usage [118]. A logic bug in a Boolean function is an example of a design fault, whereas stuck-at ...
... example , the two assertions : assert always b assert always b - - > P unbeknownst to us at that time. Figures 7.7 and 7.12. have very different meanings . The first assertion's primitives b and p are in type- writer font and are the ...
... example in Section 7.4 (Example 7.4) [28]. The authors would also like to mention the contributions made by this co-author regarding the debug enhancements [26, 28]. Many discussions helped develop and organize the de- bug enhancements ...
... example, a typical assertion can look like this: assert (result >= 0); (2.1) In this example, the line above would be placed after a certain computation in a function, whereby the integer result of a given computation should not be ...
... example of this is the Promela modeling language and the SPIN model checker [98]. Promela is a process meta language used to model finite state systems. The language allows the dynamic creation of concurrent processes and both the ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |