Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 37.
... eventually ! 7.4 Debug Enhancements for Checkers . 7.4.1 Reporting Signal Dependencies 7.4.2 Monitoring Activity ... 7.4.3 Signaling Assertion Completion . 155 156 160 162 163 163 165 7.4.4 Assertion and Cover Counters . 167 7.4.5 ...
... eventually ! Approaches Occurrence - Matching Sequences 198 199 8.6.3 Failure - Matching Sequences 200 8.6.4 Properties ..203 9 Checkers for System Verilog Assertions 207 9.1 Introduction and Overview . . . 9.2 Checker Generation for ...
... eventually! operator, when compared to the rewrite rule developed in Chapter 6. The results of all challenges are assessed empirically in Chapter 8 and in Section 9.3. In this work, a checker generator is devised with particular uses in ...
... eventually! opera- tor to various debugging enhancements related to the checkers. The enhancements can be categorized as either modifications to the behavior of checkers, or as added capabilities in the observability and the reporting ...
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |