Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 41.
... errors in real time as the design is executed, as opposed to a static result at the end of execution. Many design choices are made throughout this work to reflect these two main underlying assumptions, such that the hardware checkers ...
... errors, can cause everything from satellite and rocket malfunctions, to glitches and failures in consumer applications. One well-known case is the floating- point error found on early models of the Pentium processor by Intel. This “bug ...
... errors, whether done manually or by employing CAD tools. One can rightly talk about the verification gap (i.e. growing proportion of verification time and effort in the overall development cycle1), or even about the verification crisis ...
... errors. Engi- neers seeking to produce quality designs should use mechanisms that help find flaws in their designs, and assertions provide such mechanisms. After all, if an engineer is so confident in his or her design, there should be ...
... errors. Having a formally written set of properties upon which both teams can interact will help shorten the overall verification cycle. The method of specifying hardware designs has evolved over the years, ranging from low-level ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
Citi izdevumi - Skatīt visu
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |