Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an under-the-hood view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
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1.5. rezultāts no 60.
... checking, post-fabrication debugging, formal and dynamic verification Chapter 3: Background on regular expressions, finite automata and the different approaches to generating checkers Chapter 4: PSL and SVA assertions languages ...
... verification, the primary context that is targeted is dynamic veri- fication (ex: simulation, emulation). The checkers are designed with the goals that: (1) they should require few hardware resources when implemented in a circuit form ...
... Dynamic Verification . 2.7 Supported Simulation and Emulation Semantics . Basic Techniques Behind Assertion Checkers . 3.1 Background 3.1.1 Regular Expressions and Classical Automata 3.1.2 Automata in Model Checking . . . . 7 9 13 13 16 ...
... Dynamic Verification Static Verification Assertion Checkers in: Assertion-Based Verification (ABV) [62, 75] is emerging as the predomi- nant methodology for performing hardware verification. Assertions are high-level statements built on ...
... dynamic verification be supported? If so, how? 2. How can these checkers be enhanced and/or modified to improve the debugging process? 3. Can assertion and a checker generator be used beyond dynamic pre-fabrication verification? Most of ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
Citi izdevumi - Skatīt visu
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |