Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
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1.–5. rezultāts no 27.
... Sequences and SERES 59 4.1.3 PSL Properties 62 4.1.4 PSL Verification Directives and other Declarations 68 4.2 System Verilog Assertions ... 70 4.2.1 SVA Boolean Expressions . 73 4.2.2 SVA Sequences . 75 4.2.3 SVA Properties . 79 XV.
... Directives 152 7 Enhanced Features and Uses of PSL Checkers . 155 7.1 Introduction and Overview ... 7.2 Recursive Compilation Strategies 7.3 A Special Case for eventually ! 7.4 Debug Enhancements for Checkers . 7.4.1 Reporting Signal ...
... directives. These two chapters alone represent sufficient material to describe the PSL checker generation process, from start to finish. Enhanced features and uses of checkers are then introduced in Chapter 7. The enhancements range ...
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Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |