Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 43.
... conditions during the sabbatical leave of the second author , which included a cooperation with the IBM Haifa Research Lab that steered us into exploring assertion checkers in more depth . We are also grateful to IBM for providing us ...
... conditions or prolonged use, these are termed user faults. In modern design, the key point is that quality costs and that it must be traded for time and other company resources – the companies then need to choose between the unappealing ...
... condition that must hold throughout a function 2. assignable: specifies that a given variable can be changed 3. requires: models a pre-condition of a function 4. ensures: models a post-condition of a function Assertions in object ...
... conditions), over-specification (dead code), and violations of constraints. Among the many interesting applications of formal software verification using SPIN is the verification of many algorithms used in mis- sion critical software ...
... conditions. In silicon debugging with assertions, assertion checkers can be purposely left in the fabricated IC for debugging purposes, where they can greatly help in finding the cause of a failure. Data from Intel shows that in 2005 ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |