Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
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1.–5. rezultāts no 88.
... assertion-based verification methodology. And if you ask any project manager, “What is the biggest bottleneck in your verification flow?” you are likely to hear the response “debug ... Assertion Checkers, Marc Boul ́e and Zeljko Zilic vii.
... checker circuits from modern hardware assertion languages. Today, verification takes over 70% of the time spent in the development of modern electronic Integrated Circuits (ICs) and systems. Furthermore, the systems increasingly need to ...
... assertions more effectively as means to improve the quality of their designs, and for those wanting to know more about generating hardware assertion checkers for modern assertion languages. The book's main topics are organized as ...
... assertion checkers. We also acknowledge Katell Morin-Allory who has undertaken the computer-assisted proof of our pro- posed rewrite rules in PVS, and who also provided feedback and improvements to Subsection 6.4.5. The first author ...
... checker generator . Further , Miron Abramovici and Paul Bradley from DAFCA have provided their support and feedback on the debug applications of assertion checkers , while Alpha Oumar Barry and Parviz Yousefpour of AMD have provided ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |