Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 62.
... allow high clock speeds; and (2) that they continually report errors in real time as the design is executed, as opposed to a static result at the end of execution. Many design choices are made throughout this work to reflect these two ...
... allow the formal documentation of requirements. More details on various uses of asser- tions, including those used during the specification phase, appear in a very insightful book on assertion-based design [75]. Rapid spread of ...
... allow assertions to be used in hardware, a checker generator is re- quired to transform the assertions into circuit-level checkers. Assertions are written in high-level languages and are not suitable for direct implementation in circuit ...
... allowing certain types of properties to be used in model checkers that do not support PSL and SVA. The techniques used in developing the checker generator can further be applied to areas as diverse as hardware-accelerated pro- tein ...
... allows the dynamic creation of concurrent processes and both the synchronous and asynchronous forms of inter-process communication. The properties used for specifying correctness requirement in SPIN are specified in temporal logic ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |