Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 91.
... algorithms used to convert PSL and SVA into hardware checkers, to introducing enhancements required to improve checker de- bugging, and on to exploring checker extensions required for post-silicon assertion checking and hardware ...
... algorithms used in the checker generator, creation of checkers from automata • Chapter 6: Automata construction for PSL assertions, case study of automated reasoning about PSL semantics and rewrite rules • Chapter 7: Debug enhancements ...
... algorithm. Although the effect was barely perceptible, the flaw has caused a large recall of processors, and most esti- mates place the total cost to Intel at nearly half a billion US dollars. The recalls and product delays have ...
... algorithms, as well as with the methodologies in the use of assertions. While this book primarily focuses on the ... algorithms for converting PSL and SVA into au- tomata, and subsequently into circuits, are developed. Over 20 automata ...
... . Although Chapter 9 seems self-contained, many algorithms from the PSL chapter are re-used given the similarities between the two languages. The typographical conventions used in the book are briefly overviewed 8 1 Introduction.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |