Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring

Pirmais vāks
Springer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.

This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.

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Introduction
1
Assertions and the Verification Landscape
13
Basic Techniques Behind Assertion Checkers
37
PSL and SVA Assertion Languages
55
Automata for Assertion Checkers
83
Construction of PSL Assertion Checkers
105
Enhanced Features and Uses of PSL Checkers
155
Evaluating and Verifying PSL Assertion Checkers
179
Checkers for System Verilog Assertions
207
Conclusions and Future Work
251
A Example for UpDown Counter
259
References
265
Index
275
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