Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 37.
... MBAC checker gener- ator, were developed during the first author's Ph.D. at McGill University, of which the second author was the advisor. Montreal March 2008 Marc Boul ́e Zeljko Zilic Acknowledgements The authors would like to thank ...
... MBAC. Thanks to Stephan Bourduas, Jean-Samuel Chenard and Nathaniel Azuelos for being the first to stress the checker generator in a real-world application. We would further like to thank Dominique Borrione and Katell Morin-Allory from ...
... MBAC's usefulness in industrial verification settings . Some of the features of the tool would not be here today , while some bugs would still have persisted if it wasn't for all of them . Further , we are grateful to Pierre Paulin from ...
... MBAC. 1.2. Book. Objectives. Within the powerful emerging Assertion-Based Design paradigm, the authors feel that on the road to improved design quality there is a large number of research top- ics, dealing with core algorithms, as well as ...
... MBAC checker gen- erator produces smaller and faster circuits that offer the correct assertion behavior while supporting all simple subset operators. Chapter 9 is devoted to checker generation for SystemVerilog assertions. Section 9.2 ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |