Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 73.
... Boolean Expressions 55 58 4.1.2 PSL Sequences and SERES 59 4.1.3 PSL Properties 62 4.1.4 PSL Verification Directives and other Declarations 68 4.2 System Verilog Assertions ... 70 4.2.1 SVA Boolean Expressions . 73 4.2.2 SVA Sequences ...
... logic bug in a Boolean function is an example of a design fault, whereas stuck-at-value faults and short circuits ... expressions. Assertions can also be seen as a formal documentation language, free of the am- biguities inherent to ...
... operators is introduced in Chapter 6. The presentation starts with the lowest layer in the language structure, namely Boolean expressions, then proceeds gradually to the intermediate language layers consisting of temporal sequences and ...
... Boolean signals called b and p re- spectively . In the second assertion , the variables b and p are intended to ... expressions of the type “ a occurs ” are used , it is under- stood to mean “ when the Boolean expression a evaluates to ...
Esat sasniedzis šīs grāmatas aplūkošanas reižu limitu.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
Citi izdevumi - Skatīt visu
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |