Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
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1.–5. rezultāts no 91.
... , were developed during the first author's Ph.D. at McGill University, of which the second author was the advisor. Montreal March 2008 Marc Boul ́e Zeljko Zilic Acknowledgements The authors would like to thank Harry Foster and Preface xi.
... first to stress the checker generator in a real-world application. We would further like to thank Dominique Borrione and Katell Morin-Allory from the TIMA-VDS laboratory in France for the many interesting discussions and exchanges ...
... first author would like to thank colleagues and friends at École de technolo- gie supérieure , and in particular Patrick Cardinal and André St - Amand . The second author owes a great gratitude to Katarzyna Radecka for picking up the ...
... first of all, the product solved the right problem. This task of design validation starts with gathering and then analyzing the requirements to produce the specification for design teams, and can often be finished only after the product ...
... first two blocks in Figure 1.1, namely specification and design. The assertion's main role is in verification through simula- tion, emulation and formal verification. Synthesizing assertion-checking circuits is an effective way of ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |