VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, AustraliaRicardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer Springer, 2007. gada 1. okt. - 344 lappuses This book contains extended and revised versions of the best papers that were presented during the thirteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a Global System-on-a-Chip Design & CAD conference. The 13th conference was held at the Parmelia Hilton Hotel, Perth, Western Australia (October 17-19, 2005). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier and Darmstadt. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5, is to provide a forum to exchange ideas and show industrial and academic research results in the field of mic- electronics design. The current trend toward increasing chip integ- tion and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI-SOC conferences aim to address these exciting new issues. The 2005 edition of VLSI-SoC maintained the traditional structure, which has been successful at the previous VLSI-SOC conferences. The quality of submissions (107 papers from 26 countries) made the selection process difficult, but finally 63 papers and 25 posters were accepted for presentation in VLSI-SoC 2005. Out of the 63 full papers presented at the conference, 20 were chosen by a selection committee to have an extended and revised version included in this book. These selected papers came from Australia, Brazil, France, Germany, Italy, Korea, Portugal, Sweden, Switzerland, United Kingdom and the United States of America. x Preface |
Saturs
25 | |
Defragmentation Algorithms for Partially Reconfigurable Hardware 41 | 40 |
Technology Mapping for Area Optimized Quasi Delay Insensitive | 55 |
A Novel 3D Vertically Integrated Adaptive | 70 |
A methodology for the Implementation of Partially | 87 |
Digital Systems Based on apriori Functional FaultTolerance | 111 |
Issues in Model Reduction of Power Grids 127 | 126 |
A Traffic Injection Methodology with Support for SystemLevel | 145 |
Application to GALS | 195 |
A Novel MicroPhotonic Structure for Optical Header Recognition | 209 |
Combined Test Data Selection and Scheduling for Test Quality | 220 |
Optimization under ATE Memory Depth Constraint 221 | 240 |
Scan Cell Reordering for Peak Power Reduction during | 267 |
On The Design of A Dynamically Reconfigurable FunctionUnit | 283 |
Exact BDD Minimization for PathRelated Objective Functions 299 | 298 |
an Analog Circuit to Thwart | 317 |
Pareto Points in SRAM Design Using the Sleepy Stack Approach | 163 |
Modeling the Traffic Effect for the Application Cores Mapping | 178 |
A Transistor Placement Technique Using Genetic Algorithm | 331 |
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VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10.5 Thirteenth ... Ricardo Reis,Adam Osseiran,Hans-Joerg Pfleiderer Priekšskatījums nav pieejams - 2010 |
VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10.5 Thirteenth ... Ricardo Reis,Adam Osseiran,Hans-Joerg Pfleiderer Priekšskatījums nav pieejams - 2007 |
Bieži izmantoti vārdi un frāzes
algorithm allows analysis application approach architecture array asynchronous attack block cell circuit column communication compared complex components computation Conference configuration considered constraints consumption core correlation cost cycles defect delay described device dynamic elements energy Equation error estimation example execution fault Figure flow FPGA function gate given hardware hardware task IEEE implemented increase input integrated interconnect International interrupt leakage logic mapping memory method methodology minimization module multiplier networks node nonlinear obtained operation optical optimization output parameters partial path performance ports possible presented probability problem Proceedings proposed Quasi Delay Insensitive reconfiguration reduced represents respect scan selected sequence shown shows signal simulation sleepy stack solution SRAM cell standard structure switching Table task technique test data test vectors tool transistors transitions
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