Embedded Computing: A VLIW Approach to Architecture, Compilers and ToolsElsevier, 2005. gada 19. janv. - 712 lappuses The fact that there are more embedded computers than general-purpose computers and that we are impacted by hundreds of them every day is no longer news. What is news is that their increasing performance requirements, complexity and capabilities demand a new approach to their design. Fisher, Faraboschi, and Young describe a new age of embedded computing design, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design. They demonstrate why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses. These elements must be unified in a system design with high-performance processor architectures, microarchitectures and compilers, and with the compilation tools, debuggers and simulators needed for application development. In this landmark text, the authors apply their expertise in highly interdisciplinary hardware/software development and VLIW processors to illustrate this change in embedded computing. VLIW architectures have long been a popular choice in embedded systems design, and while VLIW is a running theme throughout the book, embedded computing is the core topic. Embedded Computing examines both in a book filled with fact and opinion based on the authors many years of R&D experience. · Complemented by a unique, professional-quality embedded tool-chain on the authors' website, http://www.vliw.org/book· Combines technical depth with real-world experience · Comprehensively explains the differences between general purpose computing systems and embedded systems at the hardware, software, tools and operating system levels. · Uses concrete examples to explain and motivate the trade-offs. |
No grāmatas satura
1.5. rezultāts no 73.
2. lappuse
... processor core. Figure 1.2, while facetious, makes this point: the seven-segment display is no longer an important thing to learn about; the processor behind it is. To gain a good grounding in embedded computing, it is important to ...
... processor core. Figure 1.2, while facetious, makes this point: the seven-segment display is no longer an important thing to learn about; the processor behind it is. To gain a good grounding in embedded computing, it is important to ...
3. lappuse
... processor expected to perform a wide variety of very different tasks is probably not embedded. Embedded processors ... core for their task but did not pick the general-purpose processor core of the time. Reasons for non-general-purpose ...
... processor expected to perform a wide variety of very different tasks is probably not embedded. Embedded processors ... core for their task but did not pick the general-purpose processor core of the time. Reasons for non-general-purpose ...
4. lappuse
... processor can provide. Cost is obvious: even the cheapest Pentium processor costs more than many consumer ... core with software may enable a much cheaper design. Further, many such processor cores can be shared across different projects ...
... processor can provide. Cost is obvious: even the cheapest Pentium processor costs more than many consumer ... core with software may enable a much cheaper design. Further, many such processor cores can be shared across different projects ...
12. lappuse
... processor will run; or it might even refer to the structure of the processor itself, in that its intended use is reflected in how the computer ... core-based ASICs. 3. Digital signal processors differ from general-purpose micros in their ...
... processor will run; or it might even refer to the structure of the processor itself, in that its intended use is reflected in how the computer ... core-based ASICs. 3. Digital signal processors differ from general-purpose micros in their ...
17. lappuse
... processor attempt to keep up with a full-rate data link, NPs deploy multiple ... core at a time. However, instead of stalling on a slow access to memory, a ... processor, further increasing the number of packets that can be processed at ...
... processor attempt to keep up with a full-rate data link, NPs deploy multiple ... core at a time. However, instead of stalling on a slow access to memory, a ... processor, further increasing the number of packets that can be processed at ...
Saturs
1 | |
45 | |
83 | |
Chapter 4 Architectural Structures in ISA Design | 125 |
Chapter 5 Microarchitecture Design | 179 |
Chapter 6 System Design and Simulation | 231 |
Chapter 7 Embedded Compiling and Toolchains | 287 |
Chapter 8 Compiling for VLIWs and ILP | 337 |
Chapter 9 The Runtime System | 399 |
Chapter 10 Application Design and Customization | 443 |
Chapter 11 Application Areas | 493 |
Appendix A The VEX System | 539 |
Appendix B Glossary | 607 |
Appendix C Bibliography | 631 |
Index | 661 |
Citi izdevumi - Skatīt visu
Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools Joseph A. Fisher,Paolo Faraboschi,Cliff Young Ierobežota priekšskatīšana - 2005 |
Embedded Computing: A Vliw Approach to Architecture, Compilers and Tools Joseph A. Fisher,Paolo Faraboschi,Cliff Young Priekšskatījums nav pieejams - 2004 |
Bieži izmantoti vārdi un frāzes
algorithms allow assembly language basic blocks bits branch bytes cache called Chapter chip CISC cluster cmpx compiled simulator complex components compression computing cost cycle datapath debugging decoding dependences described devices disk dynamic embedded domain embedded systems encoding engineering example exception execution Figure floating-point FPGA functional units general-purpose global hardware implementation inline instruction set integrated interface issue iterations Java latency load logic loop machine memory accesses micro-SIMD microarchitecture Multiflow multiple multiprocessing opcode operands operating system optimizations parallel path performance phase pointer pragma predication prefetch problem processor core region register allocation register file require RISC run-time Section single slots software pipelining specific speculation standard superscalar target task techniques tion todays toolchain types typically unrolling variable vector virtual memory VLIW VLIW architectures