Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATERudy Lauwereins, Jan Madsen Springer Science & Business Media, 2008. gada 8. janv. - 516 lappuses The Design Automation and Test in Europe, DATE, is Europe’s leading international electronic systems design conference for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. It combines the conference with Europe’s leading international ex- bition for electronic design, automation and test. To celebrate the tenth anniversary of DATE, we have compiled this book with the aim to highlight some of the most influential technical contributions from ten years of DATE. Selecting 30 papers, only 3 papers from each year, is a challenging endeavor. Although the impact of papers from the first years of DATE can be det- mined through various citation indexes, the impact from the later years still have to be seen. Together with all 10 Program Chairs, we have made a selection of the most influential papers covering the very broad range of topics which is characteristic for DATE. |
Saturs
| 3 | |
| 15 | |
| 30 | |
A Halambi P Grun V Ganesh A Khare N Dutt and A Nicolau | 47 |
A Gerstlauer H Yu and D D Gajski | 59 |
Jersak R Henia and R Ernst | 73 |
H Cho B Ravindran and E D Jensen | 86 |
Networks on Chips 105 | 103 |
B Bougard F Catthoor D C Daly A Chandrakasan and W Dehaene | 235 |
Compositional Specification of Behavioral Semantics 253 | 252 |
and Beyond 269 | 267 |
Address Bus Encoding Techniques for SystemLevel | 271 |
Multiobjective CoreBased SingleChip | 290 |
Minimum Energy FixedPriority Scheduling for Variable | 313 |
Physical Design and Validation 347 | 345 |
A B Kahng S Muddu E Sarto and R Sharma | 377 |
A Generic Architecture for OnChip PacketSwitched | 111 |
Tradeoffs in the Design of a Router with Both Guaranteed | 125 |
Exploiting the Routing Flexibility for EnergyPerformanceAware | 140 |
A Tool for Instantiating Application | 157 |
A Jalabert S Murali L Benini and G De Micheli | 172 |
Modeling Simulation and RunTime Management | 187 |
Dynamic Power Management for Nonstationary Service Requests 195 | 194 |
E Y Chung L Benini A Bogliolo and G De Micheli | 207 |
Y H Lu E Y Chung T Šimunić L Benini and G De Micheli | 221 |
A Single Photon Avalanche Diode Array Fabricated | 401 |
The Test and Verification Influential Papers in the 10 Years | 417 |
An Integrated SystemonChip Test Framework | 439 |
Efficient Spectral Techniques for Sequential ATPG | 455 |
A Fast and Robust SatSolver | 465 |
Improving Compression Ratio Area Overhead | 479 |
P T Gonciari B M AlHashimi and N Nicolici | 496 |
Appendix Shortlist of Most Influential Papers | 511 |
Citi izdevumi - Skatīt visu
Design, Automation, and Test in Europe: The Most Influential Papers of 10 ... Rudy Lauwereins,Jan Madsen Priekšskatījums nav pieejams - 2009 |
Design, Automation, and Test in Europe: The Most Influential Papers of 10 ... Rudy Lauwereins,Jan Madsen Priekšskatījums nav pieejams - 2008 |
Design, Automation, and Test in Europe: The Most Influential Papers of 10 ... Rudy Lauwereins,Jan Madsen Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
abstract activity algorithm allows analysis application approach architecture assignment Automation average behavior block buffers called changes chip circuit clauses clock combination communication compared complexity components computed connected considered consumption core corresponding cost decoder defined delay described detection distribution efficient embedded energy event example execution faults frequency function gate given guaranteed IEEE implementation improvement increase input interconnect length logic mapping memory method node objects obtained operation optimal output packet path patterns performance period possible present problem processor programs proposed reduce router routing RTOS scheduling selected semantic shown shows signal simulation single solution specification stream structure switching synthesis Table task technique test set threshold tool transition unit variable vector voltage wires
Populāri fragmenti
107. lappuse - NoCs is often a major concern, because whereas computation and storage energy greatly benefits from device scaling (smaller gates, smaller memory cells), the energy for global communication does not scale down. On the contrary, projections based on current delay optimization techniques for global wires [THEI] show that global communication on chip will require increasingly higher energy consumption.
107. lappuse - Hence, communication-energy minimization will be a growing concern in future technologies. Furthermore, network traffic control and monitoring can help in better managing the power consumed by networked computational resources. For instance, clock speed and voltage of end nodes can be varied according to available network bandwidth.
206. lappuse - References [1] L. Benini and G. De Micheli, Dynamic Power Management: Design Techniques and CAD Tools, Kluwer Academic Publishers, Dordrecht, 1998. [2] L. Benini and G. De Micheli, System level power optimization: techniques and tools, ACM Trans.
289. lappuse - L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, GLSVLSI-97: IEEE 7th Great Lakes Symposium on VLSI, pp.
219. lappuse - A Predictive System Shutdown Method for Energy Saving of Event-Driven Computation", in Proceedings of the Int.
155. lappuse - A survey of wormhole routing techniques in direct networks,
293. lappuse - The input specification of such a system is typically in the form of task graphs. A task graph is a directed acyclic graph in which each node is associated with a task and each edge is associated with the amount of data that must be transferred between the two connected tasks. The period associated with a task graph indicates the time interval after which it executes again. A hard deadline, the time by which the task associated with the node must complete its execution, exists for every sink node...
184. lappuse - M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, and R. Zafalon, Analyzing on-chip communication in a MPSoC environment, Proceedings of the Design, Automation and Test in Europe (DATE), Vol.
495. lappuse - Test vector decompression via cyclical scan chains and its application to testing corebased design", Proc.
139. lappuse - Route packets, not wires: On-chip interconnection networks", in DAC 2001.